MATLAB is renowned for algorithm exploration and development. On the other hand, Simulink is capable of performing time-based multi-domain system-level design, modelling, analysis, simulation in the graphical environment. Besides, Simulink also streamlines the development of embedded systems like FPGA and provides hardware verification or co-simulation of the user design, modelling and algorithm. With hardware co-simulation and deployment, we can obtain early customer feedback and confirmation.
Therefore, Mathworks has introduced EDA Simulator Link 3.3 with the ability of FPGA co-simulation via any of several Xilinx development boards in the Simulink environment. With EDA Simulator Link 3.3, we can:
- Develop and implement our designs on FPGAs in days or weeks rather than in months.
- Explore implementation and design trade-offs in hardware environment.
- Verify HDL system level design.
Generally, the hardware co-simulation with Xilinx FPGA board is known as FPGA-in-the-loop (FIL). EDA Simulator Link supports FIL simulation on the devices shown in Table 1.
Device Family
|
Board
|
| Spartan-6 | Spartan-6 SP605 Spartan-6 SP601 XUP Atlys Spartan-6 |
| Virtex-6 | Virtex-6 ML605 |
| Virtex-5 | Virtex-5 ML505 Virtex-5 ML506 Virtex-5 ML507 Virtex-5 XUPV5–LX110T |
| Virtex-4 | Virtex-4 ML401 Virtex-4 ML402 Virtex-4 ML403 |
Table 1: Support of Xilinx board in FIL simulation
FIL provides the capability to test our designs in real hardware for any existing HDL code (VHDL, Verilog). The HDL code can be either manually written or generated from Simulink HDL coder. FIL then performs the following process:
- Generates a Simulink FIL block that represents the HDL code
- Creates a programming file and loads the design onto an FPGA with JTAG connection
- Receive and transmits data from Simulink to the FPGA via Ethernet connection
- Verify the design in a real environment
The FIL process provides synthesis, logical mapping, PAR (place-and-route), programming file generation, and communications channel. All these capabilities are specifically designed for a particular Xilinx board.
Figure 1 demonstrates how EDA Simulator Link 3.3 communicates between Simulink and the FPGA board using FIL simulation.
Figure 1: FIL Simulation with Xilinx FPGA Board
For the purpose of better understanding of this newly introduced FIL, let’s explore the way on how the FIL works. From Figure 1, it is shown that the FIL co-simulation block (hdlduc) is the interface between the Simulink model and the executable application running on the Xilinx FPGA board. The hdlduc FIL Simulink block is generated from the Simulink block, denoted as “Filter” highlighted with blue colour.
During FIL co-simulation, Simulink simulates the design model and exports the input data to the FPGA platform via Xilinx ISE Design Suite interface. Then, the FPGA platform receives input data from the Simulink design model through Ethernet connection. After that, the Xilinx FPGA will execute and process the input data based on the algorithm of the “Filter” Simulink block. Next, the FPGA will send the data back to Simulink via Ethernet connection.
In summary, FIL co-simulation combines conventional simulation with Xilinx FPGA. It provides an alternative debugging environment so that it is possible to detect, isolate, identify and resolve bugs in the early stages.
At this point of the article, you should already understand the basic notion of FPGA-in-the-loop. To find out more on the functionalities, capabilities as well as the underlying attributes of FPGA-in-the-loop, you can visit the following site:
Article by Dr. Chong Jin Hui, Senior Application Engineer
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